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AVIX is a True Zero Latency RTOS bringing extremely fast interrupt processing with full Interrupt Handler integration.

Most RTOS’s disable interrupts sometimes up to tens of microseconds leading to a number of severe drawbacks. Interrupt latency becomes unpredictable. High interrupt rates are impossible without the risk of losing interrupts leading to application failure. Porting to a new version of the RTOS or using a new RTOS function potentially leads to application failure again because interrupt lockout times have changed. AVIX does not suffer from any of these drawbacks since it just never disables interrupts. Using AVIX your application can be fast, predictable and future proof. But there is more... AVIX is a True Zero Latency RTOS which means that although it never disables interrupts, Interrupt Handlers are allowed to use many system functions. AVIX Interrupt Handlers can be fully integrated in the application which is what you may expect from a serious RTOS. Many competing products offer Zero Latency interrupt handling implying Interrupt Handlers can be fast but not a single RTOS function is allowed to be called from such Interrupt Handlers. For application integration you are left on your own and Zero latency is nothing more than a marketing slogan offering no real advantage.

Let’s summarize the advantages of this very important feature:

  1. Incredible Performance: Interrupt Handling is fast, very fast. Never are interrupts locked out by AVIX
  2. Predictable Interrupt Latency: To analyze Interrupt latency and speed all that is needed is the hardware reference manual of the MCU.
  3. Freedom of choice: All AVIX functions can be used and upgrades can be applied without the risk of introducing application failure.

How good is interrupt performance with Zero Latency?

AVIX running on a 80 MHz PIC32MX allows an interrupt to occur every 2.5s or in other words, 400,000 interrupts per second with full communication between the ISR and a thread without losing a single interrupt! No competing product is able to reach this level of performance without loosing a lot of interrupts provided the application will work in the first place.
 

To illustrate this, use is made of a basic demo application. This application consists of a timer based ISR which fires every 2.5s. The ISR writes an integer to a pipe. The other end of the pipe is read by a thread. This thread is activated every time the pipe contains 50 integers. Meanwhile two other threads, having a higher priority, are sleeping for some time after which they read a single integer from the same pipe. The structure of this application is shown in the figure to the right.

The AVIX tracing mechanism (Thread Activation Tracing) allows realtime monitoring of the activity of this application using a Logic Analyzer. For this purpose, the ISR toggles an I/O port so the activation of the ISR can be monitored also. Finally the idle thread (the active thread when no applications threads are running) is monitored.
 

Actual interrupt rates may be lower, based on code complexity

 

The timing diagram of this application is shown in the figure to the right. Here can be seen that all three threads are running and there is even spare time allowing the idle thread to run. Move your mouse over the picture to zoom in and see the interrupts occur every 2.5s.

 

Why do competing products disable interrupts?

An RTOS contains complex internal data structures which are constantly being updated as a result of functions being called from the application. These same functions however are used by ISR’s and to protect these data structures against corruption, while being updated by a function call from a thread the RTOS simply disables interrupts. The effect of this however is that interrupt performance for most RTOSes is average and no RTOS is able to reach the interrupt performance provided by AVIX.

AVIX is based on a unique architecture which differs from that used by competing products. As a result AVIX can update its internal data structures and still allow ISR’s to use AVIX functions concurrently.

 

Do other RTOSes also offer this feature?

There are RTOSes also claiming Zero Latency interrupt handling but most of these implementations have a very severe drawback in that the ISR’s are not allowed to use RTOS functions. As a result these ISR’s are ‘stand alone’, they can not communicate with threads and when this is needed a custom mechanism must be constructed. Since one of the reasons to use an RTOS in the first place is integration between ISR’s and threads, this approach is useless and it is misleading to call this Zero Latency. An RTOS only deserves this title when it offers Zero Latency combined with full integration between the ISR and threads.

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